Some CMOS image sensors have analog-to-digital converters in parallel to each other in a column to read signals from the sensors at a high speed. Such analog-to-digital converters arranged in parallel in a column are referred to as a “column ADC”.
FIG. 15 is a schematic diagram of I/O characteristics of an analog-to-digital converter. Where the precision of an analog circuit is as ideal during amplification, a straight line is shown as indicated by 1501. In the case where a deviation is made from the ideal line as indicated by dashed lines 1502, a digital code (an erroneous code) which will not appear even if any analog data is input occurs.
As an example of a prior art against the problem, Japanese Patent Application Laid-Open No. 2006-025189 discusses an image sensor that has a circulation type of analog-to-digital converter for each column thereof and performs analog-to-digital conversion twice to reduce errors due to variations in capacitance used in the circulation type of analog-to-digital converter. The image sensor disclosed in Japanese Patent Application Laid-Open No. 2006-025189 performs analog-to-digital conversion twice while switching capacitances used in a circuit thereof and retains the converted data in a register for averaging and output.
Japanese Patent Application Laid-Open No. 2005-210480 discusses an imaging apparatus having a plurality of analog-to-digital converters that corrects output signals of the analog-to-digital converters according to a reference signal of a reference signal generating unit of generating the reference signal.    [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-025189    [Patent Document 2] Japanese Patent Application Laid-Open No. 2005-210480
However, correction according to a method being discussed in Japanese Patent Application Laid-Open No. 2006-025189 has the following three problems: The first is that analog-to-digital conversion is always required twice, which causes, in principle, a conversion speed to be lowered to ½. This problem is fatal to digital camera application requiring high-speed shutter and moving image application.
The second is that excess wiring, capacitance and switch must be arranged to switch circuitry connection. A column ADC must be laid out in almost the same width or at a maximum several times as wide as pixels of the image sensor and an increase in the number/volume of wirings, capacitance or switches will impair pixel size reduction or cause characteristic degradation.
The third is that correction is not complete. FIG. 16 is a graph illustrating a relationship between an analog input and a digital output for describing a principle thereof. By twice converting an analog-to-digital conversion characteristic indicated by alternate long and short dashed lines of 1601 and an analog-to-digital conversion characteristic indicated by dashed lines of 1602, averaging is performed, thus an ideal analog-to-digital conversion characteristic is achieved as indicated by a solid line of 1603.
For example, at a point A of 1604, the twice-conversion yields conversion results as seen from 1605 and 1606 deviated from an ideal value twice for the same analog value. By averaging the conversion results, an ideal characteristic as seen from 1607 can be achieved. However, when an analog value corresponding to a value where discontinuity of a digital output is large as indicated by a point B of 1608 enters, twice-conversion results as indicated by 1609 and 1610 will form an ideal characteristic. However, if conversion result as indicated by 1611 is obtained in place of 1610 by external disturbance due to random noise of pixels or a read-out circuit or the like, averaging will not make the obtained result meet the ideal characteristic, resulting in a correction error.
The imaging apparatus being discussed in Japanese Patent Application Laid-Open No. 2005-210480 requires one correction unit for each analog-to-digital converter. That is, a lookup table is used. The lookup table varies with individual analog-to-digital converters, which makes it difficult to realize commonality for a plurality of analog-to-digital converters.
Sensors arranged with pixels in a two-dimensional form generally produces outputs from a plurality of signal wires, finally, by multiplexing or serializing. Furthermore, in the case of a sensor having many analog-to-digital converters like a column ADC, a correction circuit is provided for each analog-to-digital converter at a previous stage at which an output is multiplexed. Accordingly, as the number of the analog-to-digital converters increases, such a sensor is difficult to apply for practical use. In particular, where a pixel region arranged with a plurality of pixels including photoelectric transfer elements and a reading unit including analog-to-digital converters are disposed on an identical semiconductor substrate, restriction on layout of elements is strict and, in some cases, an extreme increase in circuit scale causes a particular problem due to the increased number of correction circuits.
The present invention, implemented to solve at least one of the foregoing problems, is provided for the objects of complete correction with data of once analog-to-digital conversion, as much elimination of excessive use of switches, analog elements or the like as possible, and/or prevention of erroneous correction.